The present application relates to a semiconductor device using an oxide semiconductor, a display unit including the semiconductor device, and an electronic apparatus.
In an active driving type liquid crystal display unit or organic EL (electroluminescence) display unit, TFT (Thin Film Transistor) is used as a drive element, and an electrical charge corresponding to a signal voltage for writing an image is held in a capacitor. However, when a parasitic capacitance generated at an intersection region between a gate electrode and source-drain electrodes of TFT increases, a signal voltage may be varied to cause deterioration in image quality.
In particular, in the organic EL display unit, when a parasitic capacitance is large, it is necessary to increase a holding capacitance as well. Proportions occupied by wirings, etc. increase in accordance with a layout of pixels. As a result, a probability of a short circuit, etc. among wirings increases and a yield in manufacturing is reduced.
To address such issues, a method of reducing a parasitic capacitance generated at an intersection region between a gate electrode and source-drain electrodes has been proposed for TFT in which an oxide semiconductor such as a zinc oxide (ZnO) or an indium gallium zinc oxide (IGZO) is used for a channel. For example, reference is made to Japanese Unexamined Patent Application Publication No. 2007-220817 (JP2007-220817A). Also, reference is made to J. Park et al., “Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors”, Applied Physics Letters, American Institute of Physics, 2008, volume 93, 053501 (Non Patent Literature 1) and R. Hayashi et al., “Improved Amorphous In—Ga—Zn—O TFTs”, SID 08 DIGEST, 2008, 42. 1, p. 621-624 (Non Patent Literature 2).
JP2007-220817A and Non Patent Literature 1 each describe a method in which after a gate electrode and a gate insulating film are provided on a channel region of an oxide semiconductor film in the same position in plain view, a resistance of a region exposed from the gate electrode and the gate insulating film of the oxide semiconductor film is reduced to form a source-drain region (low-resistance region), i.e., each describe a top gate type TFT formed in a so-called self-alignment manner. On the other hand, Non Patent Literature 2 describes a bottom gate type TFT having a self-aligned structure, in which, in the TFT, a source-drain region is formed in an oxide semiconductor film through a backside exposure using a gate electrode as a mask.